Analog CMOS Circuit Design

Designed schematics in Cadence

We worked as a two-person team from 04.2015 to 07.2015 during my master study in University of Freiburg. The main task includes,

(i)Schematic design of a two-stage amplifier through Cadence

(ii)Tuning Circuit parameter to meet various standards e.g. Unity Gain Bandwidth, pole-zero compensation , Ac gain, Phase Margin and etc.

(iii)Conducting Monte-Carlo and Corner Simulation

Honghu Xue
Honghu Xue
PhD student

My research interests include Dep Reinforcement Learning and Deep Learning.